Gated semiconductor devices such as metal oxide semiconductor field-effect transistors (MOSFETs) are commonly formed in active isolated regions of an IC chip. In MOSFETs, dopant implanted source and drain regions (S/D) are formed in a silicon substrate with corresponding S/D terminals. MOSFETs further include raised or elevated conductive gate layer pillars on the silicon substrate for forming gate electrodes. The gate layer is comprised of conductive material such as doped or undoped polysilicon and is electrically isolated from the silicon substrate by a suitable dielectric gate insulator or oxide layer such as silicon dioxide. When a sufficiently high gate voltage is applied, an electrically conductive inversion layer or channel forms at the interface between the gate oxide layer and silicon substrate. The conductive channel extends between the source and the drain, whereby current flows through the channel when a voltage is applied between the source and drain.
The source and drain regions may be formed in the silicon substrate by dopant ion implantation with P-type or N-type impurities as is well known in the art to form NMOS or PMOS transistors, respectively.
These foregoing MOSFET devices, including the raised gate pillars, are generally produced using a combination of known photolithography, material deposition, and material removal (e.g. etching, ashing, wet stripping, etc.) fabrication steps. Fabrication processes for forming semiconductor devices such as MOSFETs may also generally include growing or forming one or more pure monocrystalline epitaxial silicon layers on the silicon substrate as is well known in the art. Epitaxial silicon layers beneficially forms uniform silicon layers of predictable electrical characteristics, thereby enhancing the integrity and performance of the resulting semiconductor device formed on the substrate.
As the size of IC chips continues to decrease, so does the size of semiconductor devices such as MOSFETs. This creates new chip fabrication challenges for producing MOSFETs of ever decreasing dimensions that remain free of defects which may degrade device performance and therefore increase chip rejection rates. The challenge of producing defect-free semiconductor devices is increasingly acute in the N20 technology node (20 nm process) and beyond.
One problem facing N20 node fabrication of MOSFET devices is silicon loss. FIG. 1 illustrates a conventional MOSFET device fabrication formation process used to make a lightly doped drain (LDD) MOSFET transistor which may experience a silicon loss defect. In LDD structures, source and drain regions near the conductive channel are less heavily doped (e.g. N-) than regions of the source and drain farther away from the channel. The lower doping near the gate electrode minimizes electric field effects near the drain, thereby improving the speed and reliability of the MOSFET transistor.
As shown in FIG. 1, the steps may sequentially include polysilicon layer etching to form gate electrode pillars, LDD ion implantation (shown in dashed lines) and subsequent photoresist (PR) stripping, offset sidewall (SW) spacer deposition and subsequent etching, source/drain (S/D) recess etching, and S/D epitaxial silicon deposition. During the various foregoing material etching and stripping operations, a reduction in the silicon substrate and gate oxide material occurs as a side effect as shown by the shallow concave depressions between the raised gate pillars). This may result in a profile wherein concave cavities or recesses are formed beneath the raised source and drain pillars between the gate oxide and substrate (see S/D Recess Etch step). During the subsequent epitaxial silicon deposition process shown in the last image of FIG. 1 (labeled S/D Epi), the silicon may not always completely fill the concave recess resulting in an unwanted void at the very inside corner of the concave recess as shown in the enlarged detail. These voids are an undesirable defect because if large enough, they may adversely affect the performance of the MOS transistor.
An improved process for producing a semiconductor device is therefore desired.